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Civil-Comp Conferences
ISSN 2753-3239
CCC: 10
PROCEEDINGS OF THE EIGHTEENTH INTERNATIONAL CONFERENCE ON CIVIL, STRUCTURAL AND ENVIRONMENTAL ENGINEERING COMPUTING
Edited by: P. Iványi, J. Kruis and B.H.V. Topping
Paper 2.5

An Offline Hardware-in-the-Loop Approach to Analyse Pantograph-Catenary Interaction

P. Antunes1,2, J.P. Santos1, J.M. Rebelo1, J. Pombo1,2,3, A. Schirrer4, S. Jakubek4, M. Tur Valiente5 and S.G. Verdú5

1Institute of Railway Research, University of Huddersfield, United Kingdom
2IDMEC - Instituto Superior Técnico, Universidade de Lisboa, Portugal
3ISEL, Instituto Politécnico de Lisboa, Portugal
4Institute of Mechanics and Mechatronics, TU Wien, Austria
5Centro de Investigacion en Ingeniería Mecánica - Departamento de Ingeniería Mecanica y de Materiales, UP Valencia, Spain

Full Bibliographic Reference for this paper
P. Antunes, J.P. Santos, J.M. Rebelo, J. Pombo, A. Schirrer, S. Jakubek, M. Tur Valiente, S.G. Verdú, "An Offline Hardware-in-the-Loop Approach to Analyse Pantograph-Catenary Interaction", in P. Iványi, J. Kruis, B.H.V. Topping, (Editors), "Proceedings of the Eighteenth International Conference on Civil, Structural and Environmental Engineering Computing", Civil-Comp Press, Edinburgh, UK, Online volume: CCC 10, Paper 2.5, 2025,
Keywords: railway dynamics, pantograph-catenary, dynamic analysis, hardware-in-the-loop, hybrid testing, finite element analysis.

Abstract
Hybrid testing enhances the development and analysis of complex mechanical systems by integrating physical experiments with computational modelling and simulation. In the field of railway dynamics, Hardware-in-the-Loop (HiL) simulation is a prominent hybrid testing technique used to investigate the interaction between the pantograph and the catenary system. Most existing pantograph–catenary HiL setups employ a real-time numerical model of the catenary, which interfaces with a physical pantograph mounted on a full-scale test bench. However, the requirement for real-time computation imposes constraints on the numerical model complexity and size. To address these limitations, this study introduces an iterative offline HiL approach. In this method, hardware testing is guided by the convergence of results across successive iterations between testing and simulation, eliminating the need for real-time simulation. The proposed methodology is validated through experimental tests experiments, where the convergence behaviour and robustness of the approach is assessed. A discussion of the advantages and limitations of both online and offline HiL methods is also discussed, along with potential directions for future development.

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