Computational & Technology Resources
an online resource for computational,
engineering & technology publications
PROCEEDINGS OF THE THIRD INTERNATIONAL CONFERENCE ON RAILWAY TECHNOLOGY: RESEARCH, DEVELOPMENT AND MAINTENANCE
Edited by: J. Pombo
Hardware in the Loop Testing as a Tool for Pantograph Virtual Homologation
A. Facchinetti and S. Bruni
Dipartimento di Meccanica, Politecnico di Milano, Italy
A. Facchinetti, S. Bruni, "Hardware in the Loop Testing as a Tool for Pantograph Virtual Homologation", in J. Pombo, (Editor), "Proceedings of the Third International Conference on Railway Technology: Research, Development and Maintenance", Civil-Comp Press, Stirlingshire, UK, Paper 262, 2016. doi:10.4203/ccp.110.262
Keywords: hardware-in-the-loop, real-time models, pantograph-catenary interaction, virtual homologation.
This paper addresses the "hardware-in-the-loop" simulation (HILS) of pantograph-catenary interaction. The paper mainly focus on "closed-loop" HILS, analysing the influence of some modelling options and reporting its validation against line measurements. The main features of the "open-loop" and "closed-loop" HIL testing approaches with respect to some typical tasks of pantograph virtual homologations and, more generally, in the perspective of supporting the development of a pantograph system, are then discussed.
purchase the full-text of this paper (price £22)