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PROCEEDINGS OF THE FIFTH INTERNATIONAL CONFERENCE ON ENGINEERING COMPUTATIONAL TECHNOLOGY
Edited by: B.H.V. Topping, G. Montero and R. Montenegro
Intrinsic Evolvable Hardware Chip Design for a Nonlinear Process Control Plant
B. Rama Murthy1, P. Subbaiah2 and I. Venu Gopal2
1Department of Instrumentation, Sri Krishna Devaraya University, Andhra Pradesh, India
B. Rama Murthy, P. Subbaiah, I. Venu Gopal, "Intrinsic Evolvable Hardware Chip Design for a Nonlinear Process Control Plant", in B.H.V. Topping, G. Montero, R. Montenegro, (Editors), "Proceedings of the Fifth International Conference on Engineering Computational Technology", Civil-Comp Press, Stirlingshire, UK, Paper 55, 2006. doi:10.4203/ccp.84.55
Keywords: evolvable hardware, nonlinear process control plant, genetic algorithm, virtual reconfigurable circuit, back propagation algorithm, sensor failures.
Process engineering, process design and simulation, process supervision, control and estimation, process fault detection and diagnosis rely on the effective processing of unpredictable and imprecise environment. A majority of applications require cooperation of two or more independently designed, separately located, but mutually affecting subsystems. In addition to good behaviour of each of the subsystems, an effective coordination is very important to achieve the desired overall performance. Such a co-ordination can permit the use of commercially designed subsystems to perform more sophisticated tasks than at present and improve the operational reliability. However, such a co-ordination is very difficult to attain mainly due to the lack of precise system models and/or dynamic parameters. In such situations, the evolvable hardware (EHW) techniques, which can achieve the sophisticated level of information processing that the brain is capable of, can excel. These techniques are also very much useful in designing fault tolerant systems. Fault tolerance is the ability of the system to function correctly even in the presence of failures. The conventional approach of designing fault tolerant systems employs redundancy techniques. It produces rather a static system that cannot adapt as more and more faults occur. Also with the increase in complexity of the system, complete fault coverage at the testing phase of the design cycle is very difficult to achieve, if not impossible. Hence designing fault tolerant systems using conventional approaches is difficult for larger systems. Hence the approach of designing fault tolerant systems using evolutionary algorithms has gained momentum. This approach can adapt to more faults as they are encountered in practice. A genetic algorithm is used here to reconfigure aspects of a circuit to counter-act any deterious faults. The idea of this work is to develop a system that is tolerant to sensor failures.
The proposed system consists of genetic algorithm (GA) to search for an optimal solution, a virtual reconfigurable circuit (VRC) and a neural network, which is used as an estimator. On comparing the estimated value and the actual value, the failure of the sensor(s) is/are detected and the evolution process is carried out to redesign the processing hardware, which is tolerant to the failure of the sensor(s). In this work, the failure is not only restricted to sensors but also failure in some parts of the processing hardware is also considered.
In this paper, a EHW based system with a neural estimator, is used, to handle exceptions such as sensor faults or extreme situations incorrectly handled by the less sophisticated conventional systems. The EHW technique based robust sensor system is built as an intrinsic evolvable hardware chip and uses a neural estimator to replace the faulty sensor value by its best estimate in the mean absolute error sense. The proposed method finds application mainly in the area of sensor validation, control engineering and other related fields to estimate the true variations of the signal during the failure period of a sensor. The estimator is designed by coordinating the data from multiple sensors, and the failure detection is accomplished by comparing the actual system output with a neural estimator output. The operation of the system is as follows: initially a processing circuit is evolved to average the input from the sensors. Then the neural estimator output is compared with the actual output. If any/two of the sensors fail, then the processing circuit is to be reprogrammed to take the average of the remaining sensors. The configuration word which is the architecture bits of the VRC is updated the moment a sensor failure is detected. The configuration word contains details about the interconnection between the processing elements (PE) of the VRC and the functional operations performed within each PE. This configuration word is regarded as the chromosome for GA which searches for the best one. In this work, the interconnection between the PEs is not restricted to its nearest neighbours.
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