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Computational Science, Engineering & Technology Series
ISSN 1759-3158
Edited by: B.H.V. Topping, P. Iványi
Chapter 2

Next Generation Processors

B. Vinter

Department of Computer Science, Copenhagen University, Denmark

Full Bibliographic Reference for this chapter
B. Vinter, "Next Generation Processors", in B.H.V. Topping, P. Iványi, (Editors), "Parallel, Distributed and Grid Computing for Engineering", Saxe-Coburg Publications, Stirlingshire, UK, Chapter 2, pp 21-36, 2009. doi:10.4203/csets.21.2
Keywords: Von Neumann barrier, next-generation processors, parallelism, multicore.

In this chapter we introduce the problems that motivate the design of the next generation processors. The continued increase of processor clock-speed is at all times crippled by inequal increasing relative time to access memory in the system. The problem, known as the Von Neumann bottleneck, has been bypassed for many years but now techniques like caching return increasingly poor benefit and new ideas are needed. The chapter looks into three different approaches to next-generation processors, the Niagara, the CELL-BE, and the Tesla, and how such processors may be programmed. In addition two approaches to programming such architectures, DSMCBE and CSP are briefly described and performance experiments are shown.

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