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Civil-Comp Conferences
ISSN 2753-3239
CCC: 12
PROCEEDINGS OF THE EIGHTH INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, GPU AND CLOUD COMPUTING FOR ENGINEERING
Edited by: P. Iványi, J. Kruis and B.H.V. Topping
Paper 2.7

Performance Constraints in IME-HEVC Software Integration

O.M. López-Granado1, M. Martínez-Rach1, H. Migallón1, R. Gutierrez Mazon2 and M. Perez Malumbres1

1Computer Engineering Department, Miguel Hernández University, Elche, Spain
2Communications Engineering Department, Miguel Hernández University, Elche, Spain

Full Bibliographic Reference for this paper
O.M. López-Granado, M. Martínez-Rach, H. Migallón, R. Gutierrez Mazon, M. Perez Malumbres, "Performance Constraints in IME-HEVC Software Integration", in P. Iványi, J. Kruis, B.H.V. Topping, (Editors), "Proceedings of the Eighth International Conference on Parallel, Distributed, GPU and Cloud Computing for Engineering", Civil-Comp Press, Edinburgh, UK, Online volume: CCC 12, Paper 2.7, 2025,
Keywords: video codecs, HEVC, FPGA, IME, temporal prediction, Sum of Absolute Difference architecture.

Abstract
High-Efficiency Video Coding (HEVC) improves compression efficiency, compared to H.264/AVC, but motion estimation remains a major computational bottleneck, especially for high-resolution video sequences. To accelerate encoding, we implemented a hardware-based motion estimation module, achieving significant speed-ups. However, integrating this hardware with software introduces constraints that may limit its impact on overall encoding performance. This paper analyzes these integration challenges, identifying key bottlenecks in the software/hardware encoding process. Based on this analysis, we propose a refined integration approach combining the hardware module with a slice-based parallel HEVC encoder. This optimized version achieves a significant speed-up of up to 146.90 times compared to the sequential HEVC encoder using full-search motion estimation.

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